Results 111 to 120 of about 2,431 (179)

E-mode digitally recessed p-NiO tri-junction HEMT with VBR of 2.5 kV [PDF]

APL Electronic Devices
In this work, an AlGaN/GaN high electron mobility transistor (HEMT) with a large positive threshold voltage (VTH) is demonstrated, based on a digitally recessed barrier combined with a p-type NiO/SiO2 gate dielectric stack to form a recessed tri-junction
Amirhossein Esteghamat, Mohammad Rezaei, Jon Elipe Fonollosa, Yuan Zong, Victor Boureau, Gulnaz Ganeeva, Elison Matioli   +6 more
doaj   +1 more source

Next generation of ICeGaNⓇ for superior no load and light load performance

Power Electronic Devices and Components
The ICeGaNⓇ technology aims at enabling widespread adoption of GaN HEMTs in power applications through a monolithic solution that offers an increased VGS(th) (2.9 V) and a wide ON-state gate driving range of 9 V to 20 V.
Kalparupa Mukherjee, Jin Zhang, Kaspars Ledins, Carlos Toyos Bada, Nirmana Perera, Loizos Efthymiou, Sheung Wai Fung, Martin Arnold, Giorgia Longobardi, Florin Udrea   +9 more
doaj   +1 more source

Simple approach to include external resistances in the Monte Carlo simulation of MESFETs and HEMTs [PDF]

, 1996
The contact and external series resistances play an important role in the performance of modern 0.1-0.2 μm HEMT's. It is not possible to include these resistances directly into the Monte Carlo simulations.
Cameron, N., Beaumont, S.P., Babiker, S., Asenov, A.   +3 more
core   +1 more source

50-nm self-aligned and 'standard' T-gate InP pHEMT comparison: the influence of parasitics on performance at the 50-nm node [PDF]

, 2006
Continued research into the development of III-V high-electron mobility transistors (HEMTs), specifically the minimization of the device gate length, has yielded the fastest performance reported for any three terminal devices to date.
Elgaid, Khaled, Moran, D.A.J., Elgaid, K., Stanley, C.R., Whyte, Griogair, Thayne, Iain, Whyte, G., McLelland, Helen, Stanley, Colin R., McLelland, H., Moran, David A. J., Thayne, I.   +11 more
core   +1 more source

Recessed and P-GaN regrowth gate development for normally-off AlGaN/GaN HEMTs [PDF]

, 2020
International audienceA new normally-off AlGaN/GaN HEMT structure is proposed. The regrowth of a P-GaN layer on the AlGaN/GaN heterostructure after the gate recess allows the achievement of the enhancement mode.
Frayssinet, Éric, Cordier, Yvon, Morancho, Frédéric, Gaëtan, Toulon, Gavelle, Mathieu, Haloui, Chaymaa, Tasselli, Josiane, Isoird, Karine   +7 more
core   +2 more sources

Characterization of a 25V GaN d-HEMT Device through Large Signal Gate Charge Measurements and In-Converter Testing [PDF]

, 2022
337343To achieve high density power conversion, the switching frequency must be increased to reduce the sizes of passive filtering components. Gallium Nitride (GaN) is a material capable of providing the improved switching characteristics, necessary for ...
Mccloskey, Paul, O’Mathuna, Cian, Fiebig, Norbert, O’Sullivan, Brendan, Benkhelifa, Fouad, O’Driscoll, Séamus   +5 more
core  

Gate Robustness and Reliability of P-Gate GaN HEMT Evaluated by a Circuit Method [PDF]

The small gate overvoltage margin is a key reliability concern of the GaN Schottky-type p-gate high electron mobility transistor (GaN SP-HEMT). Current evaluation of gate reliability in GaN SP-HEMTs relies on either the dc bias stress or pulse I-V method,
Wang, Hengyu, Wang, Bixuan, Li, Qiang, Zhang, Yuhao, Zhang, Ruizhe, He, Quanbo, Song, Qihao, Udrea, Florin   +7 more
core   +1 more source

Growth and fabrication of AlGaN/GaN HEMT based on Si(111) substrates by MOCVD [PDF]

, 2008
AlGaN/GaN high electron mobility transistor (HEMT) hetero-structures were grown on the 2-in Si (1 1 1) substrate using metal-organic chemical vapor deposition (MOCVD). Low-temperature (LT) AlN layers were inserted to relieve the tension stress during the
Luo, WJ, Chinese Acad Sci, Inst Semicond, Key Lab Semicond Mat Sci, Beijing 100083, Peoples R China. 电子邮箱地址: yuntianbb@hotmail.com, Wang, CM, Ran, JX, Liu, HX, Chen, YL, Li, JM, Xiao, HL, Li, JP, Luo, WJ, Wang, XL, Yang, FH, Guo, LC   +11 more
core  

Gate Driver Design for SiC Power MOSFETs With a Low-Voltage GaN HEMT for Switching Loss Reduction and Gate Protection [PDF]

The design of gate drivers for silicon carbide (SiC) power mosfets needs to address various adverse effects induced by the parasitic inductance in the gate loop, such as false turn-on, gate overstress, and reduced switching speed.
Zheng, Zheyang, Shu, Ji, Chen, Kevin J., Sun, Jiahui   +3 more
core   +1 more source

Analysis of RTN Induced by Forward Gate Stress in GaN HEMTs with a Schottky p-GaN Gate

2024 IEEE International Reliability Physics Symposium (IRPS)
In this work, a random telegraph noise (RTN) analysis has been carried out, to the best of our knowledge, for the first time to characterize the defects activated by forward-biased gate stress in GaN-HEMTs with metal/pGaN Schottky gate. The RTN signal has been measured for both gate leakage (IG) and drain current (ID), after each stress phase until the
Millesimo M., Fiegna C., Bakeroot B., Borga M., Posthuma N., Decoutere S., Sangiorgi E., Tallarico A. N.   +7 more
openaire   +1 more source